1. Technical Field
This invention relates in general to networking communication system and more particularly to network node attachment cards for high speed packet networks such as Asynchronous Transfer Mode (ATM) networks.
2. Prior Art
High speed networks generate problems of performance and hardware integration in the networking equipment connected to their network lines. More particularly, in the physical network lines attachment cards, the network data flows are processed at media speed before being sent to the bus of a network equipment such as a switching node or a end station.
In Asynchronous Transfer Mode (ATM) networks the attachment cards provide the physical layer and the ATM forwarder function which includes ATM processing and routing as defined in the ATM Forum specifications published by the Technical Committee.
In a network node, these problems become more crucial for implementing the support of the different types of services guaranteed to their users by the high speed network providers. At connection establishment, the user chooses between services supported by the network. Inside the network node attachment cards to connections corresponding to the different services will generate different levels of priority data flows to be processed at media speed.
This is why there is an emerging need to have in the high speed network equipment attachment cards as implementation of the multipriority processing with high performance to guarantee the quality of service. Simultaneously to this need, these equipment require hardware integration and cost saving in regards respectively with the decreasing size of equipment and the price of the hardware components. This implies the usage of designs allowing the implementation of processing sustaining the media speed while sharing hardware resources.
One constraint in network equipment attachments id the sharing between all the processes of the control blocks created at connection establishment storing connection information; these connection control blocs cannot be duplicated for evident reasons of space and cost. However, some hardware design duplicate the Logic Sections (Arithmetic and Logic Units) when more than one level of priority id to be supported for processing. As one ALU is needed per level of priority, this solution is quite expensive and does not offer a satisfying level of integration. Two other solutions for processing multipriority data flows with one ALU can be found in the network equipment today, one is the `dedicated processing without interruption`, the other one is a `comprehensive` processing. The drawbacks of the `dedicated processing without interruption` appears when a higher priority process needs to become active; it has to wait up to the completion of the lower priority process which is active. The performance if such a solution is not acceptable. One improved solution is a `comprehensive processing` which allows `on the fly` interruption of a lower priority process by a higher priority process. When a running process is interrupted `on the fly` by a higher priority process, the working data are saved. In a more complex processing environment, the higher priority tasks may comprise active and non-active states, each state corresponding to one clock cycle. Non-active or void state are lost cycles during which a result is computed or information are fetched, these operations having been started during the previous active state. As process cycles are lost, this solution is to be improved.
It is an object of the invention to provide an optimized solution for processing prioritized data flows.
It is a second object of the invention to simplify the implementation in order to have a limited number of components in a hardware implementation of the invention allowing hardware integration.